This invention relates generally to content addressable memories and specifically to improving performance of content addressable memories.
A content addressable memory (CAM) device is a storage device having an array of memory cells that can be instructed to compare the specific pattern of a comparand word with data words stored in corresponding rows of the array. During a compare operation, the comparand word is provided to the CAM array and compared with all the CAM words. For each CAM word that matches the comparand word, a corresponding match line is asserted to indicate the match result. If any of the match lines are asserted, a match flag is asserted to indicate the match condition, and a priority encoder determines the match address or index of the highest priority matching entry in the CAM array.
Typically, the match lines of the CAM array are pre-charged (e.g., to logic high) prior to the compare operation. During the compare operation, if all CAM cells in a row match the comparand data, the CAM cells do not discharge the row""s match line, which remains in its charged state to indicate a match condition for the row. Conversely, if any CAM cell in the row does not match the comparand data, the CAM cell discharges the match line (e.g., to logic low) to indicate a mismatch condition for the row. The discharged match lines are pre-charged to the supply voltage for the next compare operation.
Alternately charging and discharging the match lines in a CAM array for compare operations may result in significant power consumption. This power consumption increases as the size and/or density of the CAM array increases and, therefore, undesirably limits the memory size and the scalability of the CAM array. Thus, it would be desirable to reduce the power consumption associated with charging the match lines of a CAM array for compare operations.